The instruction set architecture is a specification of the interface to a processor implementation. In other words, it defines the instructions and format of the instructions a processor implements and can successfully use in an instruction cycle. In CPSC 213, we use a toy ISA called SM213. In reality, the vast majority of the CPUs for large devices (desktops, laptop, etc.) speak x86, and smaller devices (tablets, phones) speak ARM.
ISA Design
There are two main design philosophies when it comes to instruction set design, RISC (reduced instruction set computer) and CISC (complex instruction set computer). In general, CISC has more complex instructions that can do in one instruction what would take a RISC implementation several. This has advantages and disadvantages that are contentious and the specific definitions of RISC and CISC are not rock solid.
Historically, this ended up in RISC having simpler processor implementations, which resulted in an easier design and manufacturing process for the processor, but more intensive on the compiler and language part. This also potentially made RISC CPUs a little colder and easier on energy consumption.
CISC on the other hand made it harder for processors to be designed and built, but makes the lives of compiler engineers easier, and in general made the binary sizes of programs compiled to a CISC ISA’s smaller.
Current Day
Non-testable
Non testable but kind of cool no?
However, this is mostly relevant historically. Today, the complexity of both RISC and CISC processors has increased to the point where the complexity of designing and manufacturing RISC and CISC CPUs is not as different. CISC CPUs decode instructions into micro-ops and then run them on a RISC-like backend, so a lot of the complexity is in that decoder, but they are significantly closer in energy efficiency because of it. This is also true of the compilers for both. Both compilers for RISC and CISC are now advanced to the point where the difference in complexity is argued to be negligeable.